This invention relates to an output interface circuit and, more particularly, to an output interface circuit utilized in a logic circuit constituted by an enhancement type MOS FET (metal oxide semiconductor field effect transistor).
A circuit as shown in FIG. 1 has been used as an output interface circuit for converting a MOS logic level signal into a transistor-transistor logic (TTL) level signal.
The output interface circuit shown in FIG. 1 is constructed as follows: The gate electrode of a first enhancement type MOS FET 7 (in the following explanation it should be understood that all MOS FETs are of the enhancement type) is connected to a source terminal 6, the drain electrode is connected to a MOS level signal input terminal 1 and the source electrode is connected to a terminal 9.
The gate electrode of a second MOS FET 8 is connected to the source terminal 6, the drain electrode is connected to a MOS level signal input terminal 2, and the source electrode is connected to a terminal 10.
The gate electrode of a third MOS FET 11 is connected to terminal 9 and the drain electrode is connected to an activation signal input terminal 4, while the source electrode is connected to a terminal 13. A capacitor 15 is connected between terminals 13 and 9.
The gate electrode of a fourth MOS FET 12 is connected to terminal 10 and the drain electrode is connected to the activation signal input terminal 4, while the source electrode is connected to a terminal 14. A capacitor 16 is connected between terminals 14 and 10.
The gate electrode of a fifth MOS FET 17 is connected to a reset signal input terminal 5, the drain electrode is connected to terminal 13 and the source electrode is grounded.
The gate electrode of a sixth MOS FET 18 is connected to the reset signal input terminal 5, the drain electrode is connected to the terminal 14, and the source electrode is grounded.
The gate electrode of a seventh MOS FET 19 is connected to the terminal 14, the drain electrode is connected to the terminal 13 and the source electrode is grounded.
The gate electrode of an eighth MOS FET 20 is connected to the terminal 13, the drain electrode is connected to the terminal 14 and the source electrode is grounded.
The MOS FETs 20 and 18, and the MOS FETs 17 and 19 constitute a transfer gate circuit for executing a NOR logic function.
The drain electrode of a ninth MOS FET 21 is connected to the source terminal 6 and the gate electrode is connected to the gate electrode of the eighth MOS FET 20 (i.e.-terminal 13).
The source electrode of a tenth MOS FET 22 is grounded, while the gate electrode is connected to the gate electrode of the MOS FET 19 (i.e.-terminal 14).
The drain electrode of MOS FET 22 and the source electrode of MOS FET 21 are connected to a TTL output terminal 3 having a TTL level; the output terminal 3 is connected to external TTL circuits 23 which are connected to the output interface circuit of this invention.
The operation of the circuit shown in FIG. 1 will now be described with reference to the timing chart shown in FIG. 2 in which digits 1 through 14 represent potential levels of various terminals shown in FIG. 1.
As shown in FIG. 2, high level "1" signals are inputted to the reset signal input terminal 5 and to the MOS level signal input terminals 1 and 2, while a low level "0" signal is applied to the activation signal input terminal 4.
At this time, since MOS FETs 17 and 18 become conductive, the electric charges at terminals 13 and 14 are discharged so that these terminals would assume the ground potential. Accordingly, these MOS FETs become nonconductive, whereby the TTL level output terminal 3 assumes a floating state.
Since the gate potentials of the MOS FETs 7 and 8 are equal to the potential V.sub.DD of the source, the potentials of the terminals 9 and 10 become equal to V.sub.DD -V.sub.TH, whereby the MOS FETs 11 and 12 become conductive where V.sub.TH represents the threshold value of an enhancement type MOS FET.
Then, the signal of the reset signal input terminal 5 becomes a low level and when the MOS level signal input terminal 2 switches to a low level, the MOS FETs 17 and 18 become nonconductive while the charge on the terminal 10 discharges to assume the ground potential, thus rendering MOS FET 12 nonconductive. At this time, the potential of the terminal 9 is maintained at V.sub.DD -V.sub.TH.
Then, when a high level signal is applied to the activating signal input terminal 4, the MOS FET 11 becomes conductive, while the terminal 13 is charged to the potential V.sub.DD by the bootstrap effect of the capacitor 15.
At this time, the MOS FET 21 is conductive and the MOS FET 22 is nonconductive and the potential of the TTL level output terminal 3 becomes equal to V.sub.DD -V.sub.TH.
Consequently, when a high level logic signal at the MOS level is applied to the MOS level signal input terminal 1, a high level logic signal at a TTL level would appear on the TTL level output terminal 3.
In the same manner, when a low level signal is applied to the MOS level signal input terminal 1 and a high level signal is applied to the MOS level signal input terminal 2, a low level logic signal at a TTL level appears on the TTL logic level output terminal 3.
The prior art output interface circuit shown in FIG. 1 has the following defects when an external TTL circuit 23 judges the logic state of the TTL logic level output terminal 3.
More particularly, where the logic state of the TTL logic level output terminal 3 is at a high level, its potential is V.sub.DD -V.sub.TH so that when the source voltage V.sub.DD is lowered, the external TTL circuit 23 cannot correctly judge the logic high level. Assuming that, for example, V.sub.DD =4 V and V.sub.TH =1 V, the potential of the TTL level output terminal 3 is 3 V. Since the minimum potential of an ordinary logic high level "1" is 2.4 V, the voltage margin of the logic high level is only 0.6 V.
When a number of external TTL circuits 23 are connected to the TTL level output terminal 3 for the purpose of increasing the fan-out, the current supplied to the external TTL circuits 23 from the TTL level output terminal 3 increases, thereby lowering the potential of the output terminal 3 which makes it difficult to judge the logic high level.
When the TTL level output terminal 3 becomes a logic low level under a state in which the number of fanouts has been increased, the current supplied from the external TTL circuit 23 to the TTL level output terminal 3 increases the potential of the TTL level output terminal 3 so that the judgement of the logic low level "0" becomes difficult.
When the current capacities of the MOS FETs 21 and 22 are increased for the purpose of obviating these difficulties, the area coupled by these MOS FETs increases, thus decreasing the density of a semiconductor integrated circuit device.